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and VM_UV or CP_UV in SUP_STS are set to 1b. Normal operation resumes automatically (pre-driver, charge

pump operation and the nFAULT pin is released) once the retry time (tRETRY) lapses after VM or CP voltage

is above the corresponding under voltage rising threshold (VVM_UV or VCP_UV) as shown in Figure 8-23. The

FAULT, UVP and UV_UV or CP_UV bits stay set to 1b until a clear fault command is issued either through the

FLT_CLR bit or an nSLEEP reset pulse (tRST).

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring UVP_MODE to 00b

• Fast retry time (FAST_TRETRY) by configuring UVP_MODE to 01b

IN DRV8317H, UVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.

VUV (min) falling

VUV (max) falling

VUV (max) rising

VUV (min) rising

VVM, VCP

FETs ON

Time

FETs OFF

tRETRY

FETs ON

tRETRY

Figure 8-23. VM, CP Under Voltage Protection

8.3.11.2 VM Under Voltage Warn (VMUV_WARN) Protection

DRV8317 provides user configurable thresholds (VVMUV_WARN_FALL, VVMUV_WARN_RISE) for VM under voltage

warn protection. If at any time, voltage on VM pin falls below the VVMUV_WARN_FALL threshold, action is taken as

per VMUV_WARN_MODE configuration. There are four settings for VMUV_WARN_MODE: automatic retry with

slow and fast retry time, report only and disabled. The threshold for the VM under voltage warn fault condition

to be removed is set by VVMUV_WARN_RISE. This fault can be enabled/ disabled using VMUV_WARN_EN. In

DRV8317H, this fault is enabled by default and set to report only mode (VMUV_WARN_MODE set to 10b).

8.3.11.2.1 VM Under Voltage Warn Automatic Retry (VMUV_WARN_MODE = 00b or 01b)

After a VM under voltage warn event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low.

The FAULT, UVW bits (in DEV_STS register) and VMUV_WARN bit (in SUP_STS register) are set to 1b. Normal

operation resumes automatically (pre-driver operation and the nFAULT pin is released) once the retry time

(tRETRY) time lapses after the VM pin voltage rises above the VVMUV_WARN_RISE threshold as shown in Figure

8-24. The FAULT, UVW and VMUV_WARN bits stay set to 1b until clear fault command is issued either through

the FLT_CLR bit or an nSLEEP reset pulse (tRST).

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring VPWR_MODE to 00b

• Fast retry time (FAST_TRETRY) by configuring VPWR_MODE to 01b

DRV8317

SLVSGT3 – DECEMBER 2022

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