DRV8317 datasheet(21/69 Pages) TI

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8.3.3.1 Serial Peripheral Interface (SPI)

The SPI variant (DRV8317S) supports a serial communication bus that allows an external controller to send and

receive data with DRV8317. This enables the external controller to configure device settings and read detailed

fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

• The SCLK (serial clock) pin is an input that accepts a clock signal to determine when data is captured and

propagated on the SDI and SDO pins.

• The SDI (serial data in) pin is the data input.

• The SDO (serial data out) pin is the data output.

• The nSCS (serial chip select) pin is the chip select input. A logic low signal on this pin enables SPI

communication with the DRV8317.

For more information on the SPI, see Section 8.5.

8.3.3.2 Hardware Interface

The hardware variant (DRV8317H) replaces the four SPI pins with three resistor-configurable pins, namely,

GAIN, SLEW and MODE (one of the four SPI pins is NC in hardware variant).

PWM control mode, CSA gain and driver output slew rate can be adjusted on the hardware interface by tying

the respective pins to AGND, AVDD, pulling down to AGND with a 47-kΩ resistor or by leaving the pin floating

(Hi-Z). In DRV8317H, fault conditions are reported on the nFAULT pin, but detailed fault information is not

available.

• The GAIN pin configures the gain of the current sense amplifier.

• The SLEW pin configures the slew rate of the output voltage to motor.

• The MODE pin configures the PWM control mode.

For more information on the hardware interface, see Section 8.3.9.

Table 8-5. Hardware Pins Decode

Configuration

GAIN

SLEW

MODE

Pin tied to AGND

0.25-V/A

25-V/µs

6x PWM mode

Pin pulled to AGND via 47-kΩ

0.5-V/A

50-V/µs

6x PWM mode

Pin floating (Hi-Z)

1-V/A

125-V/µs

3x PWM mode

Pin tied to AVDD

2-V/A

200-V/µs

3x PWM mode

SPI

Interface

SDI

SDO

SCLK

nSCS

AVDD

Figure 8-5. DRV8317S SPI Interface

MODE

SLEW

GAIN

47-k

AVDD

Hardware

Interface

AVDD

Figure 8-6. DRV8317H Hardware Interface

8.3.4 AVDD Linear Voltage Regulator

A 3.3-V, 80mA linear regulator is integrated in the DRV8317 and is available to power external circuits. The

AVDD regulator is used for powering up the internal circuits of DRV8317 and can also provide power to external

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DRV8317

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