DRV8317H datasheet(32/69 Pages) TI

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IOCP

tOCP

nFAULT

Time

IOUTx

nFAULT driven low

nFAULT released

Peak current due

to deglitch time

CLR_FLT or

nSLEEP reset pulse

Figure 8-25. Over Current Protection - Latched Mode

8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)

After an OCP event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP

bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal

operation resumes automatically (pre-driver operation, the nFAULT pin is released and corresponding FETs'

OCP bits are set to 1b) after the retry time (tRETRY) time elapses. The FAULT and OCP bits stay set to 1b until

clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring OCP_MODE to 000b

• Fast retry time (FAST_TRETRY) by configuring OCP_MODE to 001b

IOCP

tOCP

nFAULT

Time

IOUTx

nFAULT driven low

nFAULT released

Peak current due

to deglitch time

tRETRY

Figure 8-26. Over Current Protection - Automatic Retry Mode

DRV8317

SLVSGT3 – DECEMBER 2022

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DRV8317H 데이터시트(PDF) 32 Page - Texas Instruments