DRV8317H datasheet(34/69 Pages) TI

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fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST). It is advisable not to

operate DRV8317 by issuing a clear fault command in the event of a OTP read fault since the register settings

may be in an unknown state and may lead to unexpected device operation.

8.3.11.7 Thermal Protection

DRV8317 has over temperature warning (OTW) and over temperature shutdown (OTS) features for protection

against over temperature events. OTW is available for FET protection (OTW_FET) while OTS is available for

FET (OTS_FET) and AVDD LDO (OTS_LDO) protection.

8.3.11.7.1 FET Over Temperature Warning (OTW_FET)

If the FET temperature exceeds the over temperature warning (TOTW_FET) threshold, the FAULT, OTF bits (in

DEV_STS register) and OTW_FET bit (in OT_STS register) are set to 1b and the nFAULT pin is driven low. The

nFAULT pin is released and OTW_FET is set to 0b once retry time (tRETRY) elapses after the FET temperature

falls below the over temperature warning (TOTW_FET - TOTW_FET_HYS) threshold. The FAULT, OTF bits stay set to

1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring OTF_MODE to 00b

• Fast retry time (FAST_TRETRY) by configuring OTF_MODE to 01b

In DRV8317H, FET over temperature warning is disabled.

8.3.11.7.2 FET Over Temperature Shutdown (OTS_FET)

If the FET temperature exceeds the shutdown threshold (TOTS_FET), all the integrated FETs are in Hi-Z, the

FAULT, OTF bits (in DEV_STS register) and OTS_FET bit (in OT_STS register) are set to 1b and the nFAULT

pin is driven low. Normal operation resumes automatically (pre-driver operation, nFAULT pin is released and

OTS_FET is set to 0b) after retry time (tRETRY) elapses, if FET temperature falls below the over temperature

shutdown (TOTS_FET - TOTS_FET_HYS) threshold. The FAULT, OTF bits stay set to 1b until cleared through the

CLR_FLT bit or an nSLEEP reset pulse (tRST). This feature cannot be disabled.

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring OTF_MODE to 00b

• Fast retry time (FAST_TRETRY) by configuring OTF_MODE to 01b

IN DRV8317H, tRETRY period is fixed at 5-ms.

8.3.11.7.3 LDO Over Temperature Shutdown

If AVDD LDO temperature exceeds the LDO over temperature shutdown (TOTS_LDO) threshold, all the

integrated FETs are in Hi-Z and device enters reset. Normal operation resumes automatically when AVDD

LDO temperature falls below the over temperature shutdown threshold (TOTS_LDO - TOTS_LDO_HYS). This feature

cannot be disabled.

8.4 Device Functional Modes

8.4.1 Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of DRV8317. When the nSLEEP pin is low, the device goes to a low-power

sleep mode. In sleep mode MOSFETs, current sense amplifiers, charge pump, AVDD regulator and SPI bus are

disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device goes to sleep

mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The tWAKE time must

elapse before the device is ready for PWM inputs.

DRV8317

SLVSGT3 – DECEMBER 2022

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