AX88780 datasheet(21/49 Pages) ASIX

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AX88780

3:1

3’b000

Reserved

R/W

Reserved, must to be 0

4.8 TXDES0--TX Descriptor0 Register

Offset Address = FC20h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

TXD0_EN

R/W

Transmit TX descriptor0

If this bit is enabled, MAC will begin to transmit data that are stored in TX

buffer. In former, data had been written to TX descriptor0. This bit will be

cleared by hardware when MAC finished the transmission.

1= enable

0= disable

14:13

2’b00

Reserved

12:0

TXD0_LEN

R/W

All 0’s

TX packet length

(unit: byte)

Driver set this field to indicate AX88780 how many bytes will be

transmitted.

4.9 TXDES1--TX Descriptor1 Register

Offset Address = FC24h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

TXD1_EN

R/W

Transmit TX descriptor1

If this bit is enabled, MAC will begin to transmit data that are stored in TX

buffer. In former, data had been written to TX descriptor1. This bit will be

cleared by hardware when MAC finished the transmission.

1= enable

0= disable

14:13

2’b00

Reserved

12:0

TXD1_LEN

R/W

All 0’s

TX packet length (unit: byte)

Driver set this field to indicate AX88780 how many bytes will be

transmitted.

4.10 TXDES2--TX Descriptor2 Register

Offset Address = FC28h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

TXD2_EN

R/W

Transmit TX descriptor2

If this bit is enabled, MAC will begin to transmit data that are stored in TX

buffer. In former, data had been written to TX descriptor2. This bit will be

cleared by hardware when MAC finished the transmission.

1= enable

0= disable

14:13

2’b00

Reserved

12:0

TXD2_LEN

R/W

All 0’s

TX packet length (unit: byte)

Driver set this field to indicate AX88780 how many bytes will be

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