PCA9420 datasheet(17/87 Pages) NXP

17 / 87 page

NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

8.11.4 BUCK1 (SW1, core buck regulator)

The SW1 supplies the core power.

Its output voltage can be programmed via I2C from 0.5 V to 1.5 V at 25 mV step and a

fixed 1.8 V, which is capable of providing up to 250 mA loading. The application circuit

uses typical 2.2 µH inductor and 10 µF/6.3 V output capacitor.

8.11.5 BUCK2 (SW2, system buck regulator)

The SW2 output voltage can be programmed via I2C register from 1.5 V to 2.1 V, or from

2.7 V to 3.3 V in both at 25 mV/step and is capable of providing up to 500 mA loading.

The application circuit uses a 2.2 µH inductor and 10 µF output capacitor.

In SW2, a pass-through mode is implemented. When its input (ASYS) is close to the

output voltage (within typical 200 mV), the SW2 enters the pass-through mode operation;

the high-side switch is fully turned on and the low-side switch is turned off, and the output

voltage can be calculated as input voltage – (RDSON*ILOAD), where RDSON is the on-

resistance of the high-side switch, and the ILOAD refers to the load current. When the

input voltage rises again, so that the voltage different between input and output crosses

the typical 250 mV threshold, the SW2 exits the pass-through mode and re- enters the

normal switching mode operation.

While SW2 operates in pass-through mode, protection features such as over-current

protection are also implemented as well.

aaa-033081

VSW2_Regulation

VPSYS2

(VPSYS2 - VSW2_Regulation)=200mV

50mV

SW2 in regulation mode

SW2 in pass-through mode

SW2 in regulation mode

Delta V=RRDS_ON_High_side x ILOAD

Delta V

Figure 8. Pass-Through mode of BUCK2 (SW2)

8.11.6 LDO1 (always-on LDO)

The LDO1 (Always-on LDO) output can be programmed from 1.7 V to 1.9 V at 25 mV

step, depending on the system requirements (selectable through I2C register). Typically,

a 1 µF/6.3 V MLCC output capacitor providing at least 1 mA loading capability is needed.

LDO1 operates based on the principle of hysteretic on/off regulation. The LDO1

output voltage is generated from a frequent activation/deactivation of the output stage

connecting VBAT to the LDO1 output depending on the programmed output voltage

for LDO1. The ripple frequency and amplitude will greatly depend on the load current

and external capacitance. The greater the load current, the higher the on/off activation

of this output stage to ensure LDO1 stays within the defined output voltage accuracy

specified in the electrical specification section. LDO1 is powered by the greater of ASYS

or VBAT_BKUP.

SW_RST event will not shut down LDO1, but sets LDO1 to default value. Watchdog

Reset will not shut down LDO1, but changes LDO1 to Mode 0 setting. SHIP mode/

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

17 / 87

PCA9420 데이터시트(PDF) 17 Page - NXP Semiconductors

PCA9420 데이터시트(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

데이터시트 다운로드

링크 URL