PCA9420 datasheet(14/87 Pages) NXP

14 / 87 page

NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

1. ON pin falling edge (filtered) applied, less than the long-press duration of time

2. A valid VIN attached. For the VIN attached plugin event, depending on

OPERATION_SEL_FROM_SHIPMODE bit setting, there are two possible operations

as described below:

a. OPERATION_SEL_FROM_SHIPMODE=0, upon VIN attached, the chip enables

the charging process, as well as start the power-up sequence for LDO1/LDO2/

SW1/SW2 per the setting

b. OPERATION_SEL_FROM_SHIPMODE=1, upon VIN attached, the chip enables

the charging process, LDO1/LDO2/SW1/SW2 remains in shutdown mode and the

chip will only enable the power-up sequence upon ON pin falling edge signal.

8.10 Watchdog timer

PCA9420 provides an on-chip watchdog timer, the duration of this watchdog can be

programmed via I2C register setting (WD_TIMER_x [1:0] in each mode configuration

registers), or disabled if needed in each mode setting.

Upon initial enable, the watchdog timer starts counting. If the watchdog timer expires

before reset, an interrupt signal is issued (WD_TIMER). Depending on the I2C register

setting (nEN_CHG_IN_WATCHDOG), the following action is also taken:

1. nEN_CHG_IN_WATCHDOG = 0: when the watchdog timer expires, the following

operations are expected.

• The SYSRSTn signal asserted (high to low)

• Charging is continued based on battery condition

• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings

2. nEN_CHG_IN_WATCHDOG=1: when the watchdog timer expires, the following

operations are expected.

• The SYSRSTn signal asserted (high to low)

• Charging is suspended

• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings

The following events reset the watchdog timer:

1. When WD_TIMER_CLR bit is set to 3b’001 at 0Dh register

2. When the device changes the mode settings

8.11 Regulators

There are four regulators on PCA9420, which include two buck regulators and two LDOs.

Table 5 shows the outline for each regulator:

Regulator name

Output regulation voltage range

Adjustable resolution

Max output current

SW1 (Core Buck)

0.5 V to 1.5 V and a fixed 1.8 V

25 mV/step

Up to 250 mA

SW2 (System Buck)

1.5 V to 2.1 V or 2.7 V to 3.3 V

25 mV/step

Up to 500 mA

LDO1 (Always-on LDO) 1.7 V to 1.9 V

25 mV/step

Up to 1 mA

LDO2 (System LDO)

1.5 V to 2.1 V or 2.7 V to 3.3 V

25 mV/step

Up to 250 mA

Table 5. Regulator summary

For each rail, its output target voltage can be set independently in mode setting 0, 1, 2 or

3. User can also choose to switch among any of the mode settings.

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

14 / 87

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