MP8798

11

Rev. 3.00

APPLICATION NOTES

Figure 14. Typical Circuit Connections

OFW

CLK

DB9 - DB0

AGND

DGND

(Substrate)

MP8798

1/2 R

Buffer

Reference

Voltage

Source

+

–

+5 V

1 of 4

Z

100W

Resistive

Isolation of

50 to 100

W

A0

A1

WR

The following information will be useful in maximizing the per-

formance of the MP8798.

2. Any input pin which can see a value outside the absolute

should be protected by diode clamps (HP5082-2835) from

input pin to the supplies. All MP8798 inputs have input pro-

tection diodes which will protect the device from short tran-

sients outside the supply ranges.

3. The design of a PC board will affect the accuracy of MP8798.

Use of wire wrap is not recommended.

properly routed and terminated. It should be shielded from

the clock and digital outputs so as to minimize cross coupling

and noise pickup.

5. The analog input should be driven by a low impedance (less

than 50

Ω).

6. Analog and digital ground planes should be substantial and

common at one point only. The ground plane should act as a

shield for parasitics and not a return path for signals. To re-

duce noise levels, use separate low impedance ground

paths.

DGND should not be shared with other digital cir-

cuitry. If separate low impedance paths cannot be provided,

DGND should be connected to AGND next to the MP8798.

7.

avoid conversion errors caused by digital supply transients.

the MP8798.

the N – doped silicon substrate. Any DC voltage difference

currents.

9. Each power supply and reference voltage pin should be

decoupled with a ceramic (0.1

µF) and a tantalum (10µF) ca-

pacitor as close to the device as possible.

10. The digital output should not drive long wires. The capacitive

coupling and reflection will contribute noise to the conver-

sion. When driving distant loads, buffers should be used.

100

Ω resistors in series with the digital outputs in some ap-