MP8798

8

Rev. 3.00

Figure 7. gives a visual definition of the INL error. The chart

shows a 3-bit converter transfer curve with greatly exaggerated

DNL errors to show the deviation of the real transfer curve from

the ideal one.

After a tester has measured all the transition voltages, the

computer draws a line parallel to the ideal transfer line. By defi-

nition the best fit line makes equal the positive and the negative

INL errors. For example, an INL error of –1 to +2 LSB’s relative

to the Ideal Line would be +1.5 LSB’s relative to the best fit line.

7

6

5

4

3

2

1

Figure 7. INL Error Calculation

Output

Codes

Analog Input (Volt)

Best Fit Line

EFS

EZS

LSB

Ideal Transfer Line

Real Transfer Line

INL

Clock and Conversion Timing

A system will clock the MP8798 continuously or it will give

clock pulses intermittently when a conversion is desired. The

timing of

Figure 8a shows normal operation, while the timing of

Figure 8b keeps the MP8798 in balance and ready to sample the

analog input.

Figure 8. Relationship of Data to Clock

CLOCK

DATA

b. Single sampling

N

N

BALANCE

CLOCK

DATA

a. Continuous sampling

N

N+1

N

N+1

Analog Input

The MP8798 has very flexible input range characteristics.

Another method is to first design the analog input circuitry and

then adjust the reference voltages for the analog input range.

One advantage is that this approach may eliminate the need for

external gain and offset adjust circuitry which may be required

by fixed input range A/Ds.

The MP8798’s performance is optimized by using analog in-

300

Ω

15 pF

Figure 9. Analog Input Equivalent Circuit

40

Ω

φ

S

60 pF

87 pF

160

Ω

4

1 pF

10 pF

Channel

Selection

4

Control

R Series

40

Ω

R MUX

500

Ω

87 pF

4 pF

+