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UPSD3422 데이터시트(PDF) 121 Page - STMicroelectronics

부품명 UPSD3422
상세설명  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 데이터시트(HTML) 121 Page - STMicroelectronics

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IrDA interface
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22.2
Pulse width selection
The IrDA interface has two ways to modulate the standard UART1 serial stream:
1.
An IrDA data pulse will have a constant pulse width for any bit time, regardless of the
selected baud rate.
2.
An IrDA data pulse will have a pulse width that is proportional to the the bit time of the
selected baud rate. In this case, an IrDA data pulse width is 3/16 of its bit time, as
shown in Figure 39 on page 119.
The PULSE bit in the SFR named IRDACON determines which method above will be used.
According to the IrDA physical layer specification, for all baud rates at 115.2k bps and below,
the minimum data pulse width is 1.41µs. For a baud rate of 115.2k bps, the maximum pulse
width 2.23µs. If a constant pulse width is to be used for all baud rates (PULSE bit = 0), the
ideal general pulse width is 1.63µs, derived from the bit time of the fastest baud rate (8.68µs
bit time for 115.2k bps rate), multiplied by the proportion, 3/16.
To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to
generate an internal reference clock, SIRClk, shown in Figure 38 on page 119. SIRClk is
derived by dividing the oscillator clock frequency, fOSC, using the five bits CDIV[4:0] in the
SFR named IRDACON. A divisor must be chosen to produce a frequency for SIRClk that
lies between 1.34 MHz and 2.13 MHz, but it is best to choose a divisor value that produces
SIRClk frequency as close to 1.83MHz as possible, because SIRClk at 1.83MHz will
produce an fixed IrDA data pulse width of 1.63µs. Table 74 provides recommended values
for CDIV[4:0] based on several different values of fOSC.
For reference, SIRClk of 2.13MHz will generate a fixed IrDA data pulse width of 1.41 µs, and
SIRClk of 1.34MHz will generate a fixed data pulse width of 2.23 µs.
Table 73.
Baud rate of UART#1 for IrDA interface
BR3
BR2
BR1
BR0
Baud rate (kbps)
00
00
115.2
00
01
57.5
00
10
38.4
00
11
19.2
01
00
14.4
01
01
12.8
01
10
9.6
01
11
7.2
10
00
4.8
10
01
3.6
10
10
2.4
10
11
1.8
11
00
1.2
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