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UPSD3422 데이터시트(PDF) 162 Page - STMicroelectronics

부품명 UPSD3422
상세설명  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 데이터시트(HTML) 162 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
USB interface
UPSD3422, UPSD3433, UPSD3434, UPSD3454
162/300
25.4.2
Endpoint FIFO pairing
Endpoint FIFOs can be paired for double buffering to provide an efficient method for bulk
data transfers. With double buffering enabled, the MCU can operate on one data packet
while another is being transferred over USB.
When two FIFOs are paired, the active FIFO is automatically toggled by the update of
USIZE. The MCU must only use the odd numbered endpoint FIFO when paired in order to
access the active FIFO. For example, if endpoints 3 and 4 OUT FIFOs are paired, the active
FIFO is accessed via endpoint 3’s OUT FIFO (see Table 102).
Table 100.
USB device address register (UADDR 0E2h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
USBADDR[6:0]
Table 101.
UADDR register bit definition
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6:0
USBADDR
R/W
USB Address of the device.
These bits are cleared with a Hardware RESET. When a USB
RESET is detected, the address register should be cleared.
Table 102.
Pairing control register (UPAIR 0E3h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
PR3OUT
PR1OUT
PR3IN
PR1IN
Table 103.
UPAIR register bit definition
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
–
–
Reserved
3PR3OUT
R/W
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s OUT FIFO.
2PR1OUT
R/W
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s OUT FIFO.
1PR3IN
R/W
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s IN FIFO.
0PR1IN
R/W
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s IN FIFO.
Obsolete
Product(s)
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