R

EM6607

Copyright © 2005, EM Microelectronic-Marin SA

14

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Debounced PA0 is connected to CPU TestVar1

Debounced PA1 is connected to CPU TestVar2

Debounced PA2 is connected to CPU TestVar3

PA[3:0]

Vdd

1

Mask

option

0

Mask

option

PortA RD

Debouncer

CPU

Testvar

Interrupt

Request

IRQpA

DebCK

IRQedgeR

1

0

1

0

debPAN

Figure 7.

Port A

Additionally, PA3 can also be used as the input terminal for the event counter.

The input port PA(0:3) has also individually selectable interrupts. Each port has its own interrupt mask bit in the MPortA

register. When an interrupt occurs, reading of the IRQpA and the IntRq registers allows identifying the source of the

interrupt. The IRQpA register is automatically cleared by reading the register or by a RESET,. Reading IRQpA register also

clears the INTPA flag in IntRq register. At initial RESET the MPortA is set to 0, thus disabling any input interrupts.

See paragraph 9 for further details about the interrupt controller.

7.1.1

PortA registers

Table 13.

PortA input status register - PortA

Bit

Name

Reset

R/W

Description

3

PA3

-

R

PA3 input status

2

PA2

-

R

PA2 input status

1

PA1

-

R

PA1 input status

0

PA0

-

R

PA0 input status

Table 14.

PortA Interrupt request register - IRQpA

Bit

Name

Reset

R/W

Description

3

IRQpa3

0

R

input PA3 interrupt request flag

2

IRQpa2

0

R

input PA2 interrupt request flag

1

IRQpa1

0

R

input PA1 interrupt request flag

0

IRQpa0

0

R

input PA0 interrupt request flag

Table 15.

PortA interrupt mask register - MportA

Bit

Name

Reset

R/W

Description

3

MPA3

0

R/W

interrupt mask for input PA3

2

MPA2

0

R/W

interrupt mask for input PA2

1

MPA1

0

R/W

interrupt mask for input PA1

0

MPA0

0

R/W

interrupt mask for input PA0