R

EM6607

Copyright © 2005, EM Microelectronic-Marin SA

17

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PC[3:0]

Vdd

2Y

2N

Mask

option

Mask

option

0

Mask

option

1

Mask

option

3Y

3N

Mask

option

Mask

option

Sleep

PortC RD

PG

NG

OE

D

Port C

CIOPC

OECsleepRes

DebCK

Debouncer

Interrupt

Request

IRQpC

IRQedgeR

1

0

1

0

debPCN

Figure 9.

Port C

If OECsleepRes bit in Option2 register is set to “1” (=6Y (Output Hi-Z in SLEEP mode)) the active Output will go tri-state when the

circuit goes into SLEEP mode. In the case of 6N - OECsleepRes at “0”, output stay active also in the SLEEP mode.

Table 22.

Option2 register - Option2

Bit

Name

Reset

R/W

Description

3

OEDsleepRes

0

W

PortD Output Enable reset by Sleep mode

2

OECsleepRes

0

W

PortC Output Enable reset by Sleep mode

1

OEBsleepRes

0

W

PortB Output Enable reset by Sleep mode

0

BuzzerPE0

0

W

Buzzer on PE0 if 1, on PB0 if 0