List of figures

Figure 1.

Logic diagram..................................................................... 2

Figure 2.

8-pin package connections, top view ..................................................... 2

Figure 3.

WLCSP connections ................................................................ 3

Figure 4.

Chip enable inputs connection ......................................................... 4

Figure 5.

Block diagram .................................................................... 6

Figure 6.

I2C bus protocol ................................................................... 7

Figure 7.

Write mode sequences with WC = 0 (data write enabled) ...................................... 11

Figure 8.

Write mode sequences with WC = 1 (data write inhibited)...................................... 12

Figure 9.

Write cycle polling flowchart using ACK .................................................. 14

Figure 10.

Read mode sequences ............................................................. 15

Figure 11.

AC measurement I/O waveform ....................................................... 20

Figure 12.

Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz

.............................................................................. 25

Figure 13.

Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz 25

Figure 14.

AC waveforms ................................................................... 26

Figure 15.

SO8N – Outline .................................................................. 28

Figure 16.

SO8N - Recommended footprint ....................................................... 29

Figure 17.

WLCSP8 - Outline................................................................. 30

Figure 18.

WLCSP8 - Recommended footprint..................................................... 31

M24M02-DR M24M02-R

List of figures

DS7025 - Rev 11

page 39/40