STE2004DIE2 datasheet(32/66 Pages) STMICROELECTRONICS

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STE2004

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Figure 40. 3-lines SPI Reading Sequence

4.2.3 3-lines 9 bits Serial Interface

The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application

supervisor.

It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals (SCLK) and one

for peripheral enable (CS).

The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral

power consumption is zero. While CS pin is high the serial interface is kept in reset.

The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from

the master.

Information are exchanged word-wide. The word is composed by 9 bit. The first bit is named SD/C and

indicates whether the following byte is a command (SD/C =0) or Data Byte (SD/C =1). During data trans-

fer, the data line is sampled on the positive SCLK edge.

If CS stays low after the last bit of a command/data byte, the serial interface expects the SD/C Bit of the

next word at the next SCLK positive edge.

A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the in-

ternal registers are cleared.

If CS is low after the positive edge of RES, the serial interface is ready to receive data.

Throughout SDOUT can be read only the driver I2C slave address or the status byte. The Command sequence

that allows to read I2C slave address or Status byte is reported in Fig. 43 & 44. SDOUT is in High impedance

in steady state and during data write.

It is possible to short circuit SDOUT and SDIN and read I2C address or status byte without any additional line.

READING SEQUENCE

Set Co bit =1, D/C Bit =0 R/W Bit =1

Source 8 pulses on SCLK and

Read the ID-Number or the Status Byte On SDOUT

END OF READING SEQUENCE

SDOUT Buffer Configured in High Impedence

LR0079

SDOUT Buffer become active (Low Impedence)

note: 1) these data are not read by the display Diver

2) SDIN and SDOUT can be short circuited if the processor can configure

serial output buffers in high impedence during data read

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