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ADC34RF52 데이터시트(PDF) 48 Page - Texas Instruments

부품명 ADC34RF52
상세설명  ADC34RF52 Quad Channel 14-bit 1.5-GSPS RF Sampling Data Converter
PDF  105 Pages
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홈페이지  http://www.ti.com
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ADC34RF52 데이터시트(HTML) 48 Page - Texas Instruments

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7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
Table 7-30 lists the available JESD204B formats and corresponding valid sampling rate ranges for the
ADC34RF52. The sampling rates are limited by the minimum and maximum SERDES line rate as well as
ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 7-31.
Table 7-30. JESD Mode Options: Real Decimation
DECIMATION
SETTING D
(complex)
L
M
F
S
MIN FS
(Gsps)
MAX FS
(Gsps)
RATIO
[fSERDES/(FS/D)]
/4
8
4
2
2
0.5
1.5
10
/8
/16
0.8
/4
4
4
2
1
0.5
1.5
20
/8
/16
/32
0.8
/4
2
4
4
1
0.5
1.3
40
/8
1.5
/16
/32
/64
0.8
/8
1
4
8
1
0.5
1.3
80
/16
1.5
/32
/64
/128
0.8
Table 7-31. JESD Sample Frame Assembly: Real Decimation - Single Band
OUTPUT
LANE
LMFS = 8422
LMFS = 4421
LMFS = 2441
LMFS = 1481
DOUT0
A0
[15:8]
A0
[7:0]
A0
[15:8]
A0
[7:0]
A0
[15:8]
A0
[7:0]
B0
[15:8]
B0
[7:0]
A0
[15:8]
A0
[7:0]
B0
[15:8]
B0
[7:0]
C0
[15:8]
C0
[7:0]
D0
[15:8]
D0
[7:0]
DOUT1
A1
[15:8]
A1
[7:0]
B0
[15:8]
B0
[7:0]
C0
[15:8]
C0
[7:0]
D0
[15:8]
D0
[7:0]
DOUT2
B0
[15:8]
B0
[7:0]
C0
[15:8]
C0
[7:0]
DOUT3
B1
[15:8]
B1
[7:0]
D0
[15:8]
D0
[7:0]
DOUT4
C0
[15:8]
C0
[7:0]
DOUT5
C1
[15:8]
C1
[7:0]
DOUT6
D0
[15:8]
D0
[7:0]
DOUT7
D1
[15:8]
D1
[7:0]
ADC34RF52
SBASAI7 – MARCH 2023
www.ti.com
48
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Product Folder Links: ADC34RF52



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