68HC705JB2 datasheet(32/128 Pages) NXP

32 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

INTERRUPTS

MC68HC705JB2

4-2

REV 1.1

An RTI instruction is used to signify when the interrupt software service routine is

completed. The RTI instruction causes the register contents to be recovered from

the stack and normal processing to resume at the next instruction that was to be

executed when the interrupt took place. Figure 4-1 shows the sequence of events

that occur during interrupt processing.

4.2

RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted

upon in a similar manner as shown in Figure 4-1. A low level input on the RESET

pin or an internally generated RST signal causes the program to vector to its

starting address which is speciﬁed by the contents of memory locations $1FFE

and $1FFF. The I-bit in the condition code register is also set.

Table 4-1. Reset/Interrupt Vector Addresses

Function

Source

Control

Bit

Global

Hardware

Mask

Local

Software

Mask

Priority

(1 = Highest)

Vector

Address

Reset

Power-On Logic

RESET Pin

Low Voltage Reset

Illegal Address Reset

USB Reset

—

$1FFE–$1FFF

Software

Interrupt (SWI)

User Code

—

Same Priority

As Instruction

$1FFC–$1FFD

External

Interrupt (IRQ)

IRQ Pin

—

I Bit

IRQE Bit

$1FFA–$1FFB

USB

Interrupts

TXD0F

TXD1F

RESUMF

—

I Bit

TXD0IE

TXD1IE

—

$1FF8–$1FF9

Timer1

Interrupts

ICF Bit

OCF Bit

TOF Bit

—

I Bit

ICIE Bit

OCIE Bit

TOIE Bit

$1FF6–$1FF7

MFT

Interrupts

TOF Bit

RTIF

—

I Bit

TOFE Bit

RTIE Bit

$1FF4–$1FF5

Reserved

$1FF2–$1FF3

Reserved

$1FF0–$1FF1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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