68HC705JB2 datasheet(65/128 Pages) NXP

65 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

PROGRAMMABLE TIMER

REV 1.1

9-7

Software can use the output compare register to measure time periods, to

generate timing delays, or to generate a pulse of speciﬁc duration or a pulse train

of speciﬁc frequency and duty cycle.

Writing to the OCRH before writing to the OCRL inhibits timer compares until the

OCRL is written. Reading or writing to the OCRL after reading the TSR will clear

the output compare ﬂag bit (OCF).

Figure 9-8. Timer Output Compare Block Diagram

To prevent OCF from being set between the time it is read and the time the output

compare registers are updated, use the following procedure:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OCRH

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

$0016

reset:

UUUUUUUU

OCRL

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

$0017

reset:

UUUUUUUU

U = UNAFFECTED BY RESET

Figure 9-9. Output Compare Registers (OCRH, OCRL)

OCRH ($0016)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OUTPUT COMPARE

RESET

CLOCK

INTERRUPT

OCRL ($0017)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

R/W

OCRH

R/W

OCRL

BUS

16-BIT COMPARATOR

(OCF)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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