C5NPARCH-RMSLASHD datasheet(30/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

Pin Descriptions Grouped

by Function

The C-5e NP pins are categorized in groups, reflecting interfaces to the chip:

• Clock Signals

• CP Interface Signals

• Executive Processor System Interface Signals

• Fabric Processor Interface Signals

• BMU SDRAM Interface Signals

• TLU SRAM Interface Signals

• QMU SRAM (Internal Mode) Interface Signals

• QMU to Q-5 TMC (External Mode) Interface Signals

• Power Supply Signals

• Test Signals

• No Connection Pins

Pins conform to Joint Electronic Devices Engineering Council (JEDEC) standards.

LVTTL and LVPECL

Specifications

C-5e NP pins are the following types:

• Low Voltage TTL-Compatible (LVTTL). The C-5e NP’s LVTTL pins conform to the JEDEC

JESD8-B specification.

• Low Voltage Positive Emitter Coupled Logic (LVPECL).

All of the signals in the following tables in this chapter denote whether the individual

signal is an Input (I), Output (O), both Input and Output (I/O), or power (P). In addition, a

PU, PD, and nc are used. The PU indicates that an internal resistor will pullup the pad if

left unconnected. PD indicates an internal pulldown resistor. NC means the pad is to be

left unconnected.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5NPARCH-RM/D 데이터시트(PDF) 30 Page - NXP Semiconductors