M5CAARCH-RMSLASHD datasheet(54/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

TLU SRAM Interface

Signals

The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 133MHz

using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to

64Mbits. The TLU SRAM interface signals are described in Table 26.

Table 26 TLU SRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

TD0 - TD63

G6, G7, G8, G9, G10, H1, H2, H3, H4, H5, H6, H7, H8,

H9, J1, J3, J4, J5, J7, J8, J9, K1, K2, K4, K5, K6, K8, K9,

L1, L2, L3, L4, L5, L6, L7, L8, L9, M1, M2, M3, M4,

M5, M6, M7, M8, M9, N1, N3, N4, N5, N7, N8, N9,

P1, P2, P4, P5, P6, P8, P9, R6, R7, R8, R9

LVTTL

PD/O TLU Memory Data

TA0 - TA21

T1, U1, U3, U4, U5, U7, U8, U9, V1, V2, V4, V5, V6,

V8, V9, W1, W2, W3, W4, W5, W6, W7

LVTTL

TLU Memory Address

TPAR0 - TPAR3

R2, R3, R4, R5

LVTTL

PD/O Word Data Parity (i.e. TPAR0 across

TD15:0)

TCE0X - TCE3X

T2, T3, T4, T5

LVTTL

TLU Memory Chip Enable

TWE0X - TWE3X

T6, T7, T8, T9

LVTTL

TLU Memory Write Enable

TCLKI

LVTTL

TLU Clock Input

TOTAL PINS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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