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M5CAARCH-RM/D 데이터시트(PDF) 89 Page - NXP Semiconductors |
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M5CAARCH-RM/D 데이터시트(HTML) 89 Page - NXP Semiconductors |
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89 / 114 page ![]() AC Timing Specifications 89 03 Executive Processor Timing Specifications The XP timing specifications include: • PCI Timing Specifications • MDIO Serial Interface Timing Specifications • Low Speed Serial Interface Timing Specifications • PROM Interface Timing Specifications PCI Timing Specifications The PCI timing is shown in Figure 19 and described in Table 48. Figure 19 PCI Timing Diagram PCLK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 PAD/P_ctl (output) PAD/P_ctl (input) PGNTX (input) PIDSEL (input) Tpc Tpao Tpav Tpaz Tpas Tpah Tpgs Tpgh Tpis Tpih Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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