PLL BUILDING BLOCK

MDS 673-01 L

4

Revision 051310

www.idt.com

ICS673-01

AC Electrical Characteristics

VDD = 3.3V ±5%, Ambient Temperature -40 to +85

° C, CLOAD at CLK = 15 pF, unless stated otherwise

VDD = 5.0V ±10%, Ambient Temperature -40 to +85

° C, CLOAD at CLK = 15 pF, unless stated otherwise

Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.

External Components

The ICS673-01 requires a minimum number of external

components for proper operation. A decoupling

capacitor of 0.01

μF should be connected between VDD

and GND as close to the ICS673-01 as possible. A

series termination resistor of 33

Ω may be used at the

clock output.

Special considerations must be made in choosing loop

components CS and CP. These can be found online at

http://www.idt.com

Avoiding PLL Lockup

In some applications, the ICS673-01 can “lock up” at

the maximum VCO frequency. This is usually caused

by power supply glitches or a very slow power supply

ramp. This situation also occurs if the external divider

starts to fail at high input frequencies. The usual failure

mode of a divider circuit is that the output of the divider

begins to miss clock edges. The phase detector

interprets this as a too low output frequency and

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Output Clock Frequency

(from pin CLK)

fCLK

SEL = 1

1

100

MHz

SEL = 0

0.25

25

MHz

Input Clock Frequency

(into pins REFIN or FBIN)

fREF

Note 1

8

MHz

Output Rise Time

tOR

0.8 to 2.0V

1.2

2

ns

Output Fall Time

tOF

2.0 to 0.8V

0.75

1.5

ns

Output Clock Duty Cycle

tDC

At VDD/2

40

50

60

%

Jitter, Absolute peak-to-peak

tJ

250

ps

VCO Gain

KO

190

MHz/V

Charge Pump Current

Icp

2.5

μA

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Output Clock Frequency

(from pin CLK)

fCLK

SEL = 1

1

120

MHz

SEL = 0

0.25

30

MHz

Input Clock Frequency

(into pins REFIN or FBIN)

fREF

Note 1

8

MHz

Output Rise Time

tOR

0.8 to 2.0V

0.5

1

ns

Output Fall Time

tOF

2.0 to 0.8V

0.5

1

ns

Output Clock Duty Cycle

tDC

At VDD/2

45

50

55

%

Jitter, Absolute peak-to-peak

tJ

150

ps

VCO Gain

KO

190

MHz/V

Charge Pump Current

Icp

2.4

μA