PLL BUILDING BLOCK

MDS 673-01 L

6

Revision 051310

www.idt.com

ICS673-01

might be 0.5 V below VDD. Hysteresis should be added

to the circuit by connecting R4.

The CLK output frequency may be up to 2x the

maximum Output Clock Frequency listed in the AC

Electrical Characteristics above when the device is in

an unlocked condition. Make sure that the external

divider can operate up to this frequency.

Explanation of Operation

The ICS673-01 is a PLL building block circuit that

includes an integrated VCO with a wide operating

range. The device uses external PLL loop filter

components which through proper configuration allow

for low input clock reference frequencies, such as a

15.7 kHz Hsync input.

The phase/frequency detector compares the falling

edges of the clocks inputted to FBIN and REFIN. It then

generates an error signal to the charge pump, which

produces a charge proportional to this error. The

external loop filter integrates this charge, producing a

voltage that then controls the frequency of the VCO.

This process continues until the edges of FBIN are

aligned with the edges of the REFIN clock, at which

point the output frequency will be locked to the input

frequency.

Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.

Figure 2. Using an External Comparator

to Reset the VCO

CHGP VCOIN

R

Z

C

1

C

2

CAP

+

-

R

4

R

2

R

3

PD

ICS673-01

REFIN

+3.3 or 5 V

SEL

VDD

0.01

μF

FBIN

200 kHz

100

Digital Divider

such as ICS674-01

GND

CLK2

CAP

20 MHz

VCOIN

C

1

R

Z

C

2

200 kHz

OE PD

40 MHz

CLK1