PLL BUILDING BLOCK

MDS 673-01 L

2

Revision 051310

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ICS673-01

Pin Assignment

VCO Predivide Select Table

0 = connect pin directly to ground

1 = connect pin directly to VDD

Pin Descriptions

12

1

11

2

10

FB IN

RE F IN

3

9

VD D

4

VD D

NC

5

GN D

6

CL K 1

7

GN D

8

GN D

CL K 2

PD

SEL

CH G P

OE

VC O IN

CA P

16

15

14

13

16 p in narro w (150 m il) S O IC

SEL

VCO Predivide

04

11

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

FBIN

Input

Feedback clock input. Connect the feedback clock to this pin. Falling

edge triggered.

2

VDD

Power

Connect to +3.3 V or +5 V and to VDD on pin 3.

3

VDD

Power

Connect to VDD on pin 2.

4

GND

Power

Connect to ground.

5

GND

Power

Connect to ground.

6

GND

Power

Connect to ground.

7

CHGP

Output

Charge pump output. Connect to VCOIN under normal operation.

8

VCOIN

Input

Input to internal VCO.

9

CAP

Input

Loop filter return.

10

OE

Input

Output enable. Active when high. Tri-states both outputs when low.

11

SEL

Input

Select pin for VCO predivide to feedback divider per table above.

12

PD

Input

Power down. Turns off entire chip when pin is low. Outputs stop low.

13

CLK2

Output

Clock output 2. Low skew divide by two version of CLK1.

14

CLK1

Output

Clock output 1.

15

NC

-

No connect. Nothing is connected internally to this pin.

16

REFIN

Input

Reference input. Connect reference clock to this pin. Falling edge is

triggered.