DS0128 datasheet(30/140 Pages) MICROSEMI

30 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.5.3

Tristate Buffer and AC Loading

The tristate path for enable path loadings is described in the respective specifications. The following

figure shows the methodology of characterization illustrated by the enable path test point.

Figure 5 •

Tristate Buffer for Enable Path Test Point

2.3.5.4

I/O Speeds

This section describes the maximum data rate summary of I/O in worst-case industrial conditions. See

the individual I/O standards for operating conditions.

Table 18 •

Maximum Data Rate Summary Table for Single-Ended I/O in Worst-Case

Industrial Conditions

I/O

MSIO

MSIOD

DDRIO

Unit

PCI 3.3 V

630

Mbps

LVTTL 3.3 V

600

Mbps

LVCMOS 3.3 V

600

Mbps

LVCMOS 2.5 V

410

420

400

Mbps

LVCMOS 1.8 V

295

400

Mbps

LVCMOS 1.5 V

160

220

235

Mbps

LVCMOS 1.2 V

120

160

200

Mbps

LPDDR-LVCMOS 1.8 V mode

400

Mbps

THZ

TZH

TLZ

90% VDDI

10% VDDI

50%

PAD

Data

(D)

Enable

(E)

50%

10% VDDI

TZL

50%

PAD

OUT

TZL, TZH, THZ, TLZ

Rent to GND for TZH, THZ

50%

Cent TZL, TLZ, TZH, THZ

Rent to VDDI for TZL, TLZ

DS0128 데이터시트(PDF) 30 Page - Microsemi Corporation

DS0128 데이터시트(HTML) 30 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL