DS0128 datasheet(85/140 Pages) MICROSEMI

85 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.10

Logic Element Specifications

2.3.10.1 4-input LUT (LUT-4)

The IGLOO2 and SmartFusion2 SoC FPGAs offer a fully permutable 4-input LUT. In this section, timing

characteristics are presented for a sample of the library. For more details, see SmartFusion2 and

IGLOO2 Macro Library Guide.

Figure 14 • LUT-4

TDDROWAL

Asynchronous load minimum pulse width for output

DDR

C, C

0.304

0.357

TDDROCKMPWH Clock minimum pulse width high for the output DDR E, E

0.075

0.088

TDDROCKMPWL

Clock minimum pulse width low for the output DDR E, E

0.159

0.187

Table 222 • Output DDR Propagation Delays (continued)

Symbol

Description

Measuring Nodes

(from, to)

–1

–Std

Unit

TPD

PAD

D/S (where

applicable)

AND4 OR

Any

Combinational

Logic

PAD

TPD

VDD

TPD

(RR)

A, B, C, D, S

OUT

50%

GND

(FF)

50%

GND

(RF)

50%

TPD = Max(tPD(RR), TPD(RF), TPD(FF), TPD(FR))

where edges are applicable for the particular

combinatorial cell

(FR)

50%

OUT

GND

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