Figure 11. High voltage start-up generator: internal schematic and pin configuration

Driver

G

S

D

LS

GaN

Sense-EN

Lin Reg

DRAIN

HV

DRV

HVclamp

VDD

SW1

SW2

IOVP

BR

RHV

RiOVP

RBR

SW3

VBUS

Transformer’s

Primary

Inductance

SGND

Cvcc

Cdrv

ICHarge

UVLO

Logic

CHV

CBR

GND

Once VDD reaches the VDD-ONREG threshold, the linear regulator that feeds the DRV pin is turned on and DRV

voltage is charged.

Once VDD reaches the start-up threshold VDD-ON:

1.

The control logic disables the internal current generator;

2.

The switch SW1 is open and the HV pin is clamped to 27 V through HVclamp;

3.

The switch SW2 is closed to pull the GaN gate to zero;

4.

The switch SW3 is closed, internally connecting the pins HV and iOVP;

5.

Finally, the LS MOSFET is turned on and its drain-to-source resistance RDS(ON)LS is used as sense resistor.

The switching activity can commence only if VDRV is higher than the VDRV-OK threshold.

The DRV pin voltage is not upper limited, but the driver does not transfer gate signal if VDRV is accidentally set to

a voltage higher than 7 V typ.

The DRV linear regulator could experience voltage drops due to insufficient VDD or excess of loading. To avoid

incorrect GaN driving, the switching activity is interrupted if VDRV drops below (VDRV-OK – Hysteresis).

In case of VDD reduction below VDD-off, the switching activity is immediately interrupted and the GaN is converted

to operate as high voltage startup.

The UVLO threshold is used to completely reset the internal logic when crossed downwards.

While the current generator is off, the residual consumption is few mWs depending on the value of the resistor

RHV; values in the range 10 to 30 MΩ help to minimize the residual losses, even if lower values may be required if

the IC must operate at extremely low input voltage.

At power-down, the converter activity stops as the input voltage falls below VSTART and VDD below VDD-OFF.

VIPERGAN100

High voltage start-up generator and supply structures

DS14000 - Rev 1

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