Figure 26. OVP timing diagram

5.12

Input OVP protection

The input overvoltage protection is intended to protect the converter in case of overvoltage on the main line,

which can cause exceeding of the GaN’s breakdown voltage. It can be easily realized connecting iOVP to the

voltage to be monitored (usually the DC rectified input mains) through a voltage divider.

When the iOVP pin voltage exceeds the internal threshold ViOVP_th (5 V typ.), for a time greater than TiOVP (250

μs typ.), the IC is shut down, while VDD is recycled between VDD-RESTART and VDD_ON by the periodical activation

of the internal HV current source. Switching is resumed when ViOVP falls below ViOVP_th.

The delay time TiOVP is intended to filter out possible disturbances that may be coupled during operations: it is

implemented through an up/down counter which is incremented when ViOVP exceeds ViOVP_th and decremented

otherwise, on a cycle-by-cycle base. In this way, temporary disturbances can be distinguished from a real

overvoltage, with great advantage to the operative continuity.

Regarding the setting, different configurations are possible, depending on whether brown-in/brown-out protection

(described in the following section) is also implemented or not, as shown in Table 1 and Figure 1.

The resistors of the voltage divider are calculated through equations () and (). The function can be disabled

connecting iOVP to GND.

5.13

Brown-In and Brown-Out protection

The brown-in protection is used to define the minimum input voltage from which the converter starts to operate.

Similarly, the brown-out protection defines the minimum input voltage below which the converter stops operating.

There are several reasons why it may be desirable to disable the converter below a certain input voltage range.

Firstly, a very low input voltage may cause overheating of the primary power section due to an excess of RMS

current. Secondly, spurious restarts may occur during converter power-down, which causes the output voltage not

to decay to zero monotonically.

At power-up, as VIN > VSTART, the internal HV-current source is activated, and the capacitor connected to VDD

is charged to VDD-ON. During this charging phase, the current IBR-DIS = 15 uA is sourced from BR and VBR is

monitored.

If VBR < VBR-DIS (100 mV, typ.), BR is assumed to be connected to GND, the related circuitry is disabled, the

information is latched until next power-on and the IC is allowed to start-up.

If VBR > VBR-DIS, the IC starts up and is allowed to switch for 30 msec. After that, if VBR > VBR-OUT (0.4 V, typ.),

it continues switching, otherwise it is disabled. From this latter case, if VBR exceeds VBR-IN (0.5 V, typ.) for more

than TBR_IN (250 usec, typ.), the IC is allowed to resume switching (brown-in); then, if VBR falls below VBR-OUT for

more than TBR_OUT (30 msec, typ.), the IC is disabled (brown-out).

The delay times are implemented through up/down counters, to reject temporary disturbances across the line.

TBR_OUT is also intended to avoid false protection triggerings due to the input capacitor voltage ripple and to

guarantee some hold-up in case of a missing cycle of the input line.

Input OVP, brown-in and brown-out conditions can be set connecting a voltage divider across the rectified input

mains, iOVP, BR and GND and selecting the resistor values according to the equations below.

VIPERGAN100

Input OVP protection

DS14000 - Rev 1

page 22/35