STM32C011D4U6 datasheet(18/94 Pages) STMICROELECTRONICS

18 / 94 page

Functional overview

STM32C011x4/x6

18/94

DS13866 Rev 3

–

Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

–

Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

–

Support of transfers from/to peripherals to/from memory with circular buffer

management

–

Programmable number of data to be transferred: 0 to 216 - 1

•

Generation of an interrupt request per channel. Each interrupt request originates from

any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12

DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the

peripherals and the DMA controller. Each channel selects a unique DMA request line,

unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its

input trigger signals.

3.13

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called

exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

and an extended interrupt/event controller (EXTI) are the assets contributing to handling the

exceptions. Exceptions include core-internal events such as, for example, a division by zero

and, core-external events such as logical level changes on physical lines. Exceptions result

in interrupting the program flow, executing an interrupt service routine (ISR) then resuming

the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon

program interrupt and unstacked upon program resume, by hardware. This avoids context

stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving

time, code and power. The ability to abandon and restart load-multiple and store-multiple

operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1

Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It

handles physical line events associated with a non-maskable interrupt (NMI) and maskable

interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between

interrupt events and start of corresponding interrupt service routines (ISRs). The ISR

vectors are listed in a vector table, stored in the NVIC at a base address. The vector

address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring

just before is waiting for being served, the later-arriving higher-priority interrupt event is

served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

STM32C011D4U6 데이터시트(PDF) 18 Page - STMicroelectronics

STM32C011D4U6 데이터시트(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

데이터시트 다운로드

링크 URL