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S12MSCANV2/D 데이터시트(PDF) 41 Page - NXP Semiconductors

부품명 S12MSCANV2/D
상세설명  The SoC Guide provides information about the MC9S12KG128 device made up of standard HCS12 blocks and the HCS12 processor core
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MC9S12KG128 SoC Guide — V01.01
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12KG128. Each mode has an
associated default memory map and external bus configuration.. In addition each operating mode, with the
exception of Special Peripheral Mode(SPM), can be configured for low power operation by entering one
of three low power sub-modes. The device is also equipped with security features which restrict certain
modes of operation and limit access to internal memory. More detailed information on the various
operating modes, and their configurations can be found in the HCS12 Core User Guide.
4.2 Modes of Operation
There are two basic categories of operating modes:
1.
Normal modes: Some registers and bits are protected against accidental changes.
2.
Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
In all Normal and Special modes a system development and debug feature, background debug mode
(BDM), is available. In special single-chip mode, BDM is active immediately after reset.
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The MODA and MODB pins are not
available in the 80 pin package versions and are pulled down internally, restricting the mode selection out
of reset to Single Chip Modes. When reseting into all modes except SPM, the ESTR bit in the EBICTL
register is set to one, configuring the ECLK as a bus control signal, to assure that the reset vector can be
fetched even if it located in an external slow memory device.
Table 4-1 Mode Selection
MODC
MODB
MODA
Mode Description
Notes
000
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
Available in all
package versions
0
0
1
Emulation Expanded Narrow, BDM allowed
Only available in
112 LQFP
0
1
0
Special Test (Expanded Wide), BDM allowed
Only available in
112 LQFP
0
1
1
Emulation Expanded Wide, BDM allowed
Only available in
112 LQFP
1
0
0
Normal Single Chip, BDM allowed
Available in all
package versions
1
0
1
Normal Expanded Narrow, BDM allowed
Only available in
112 LQFP
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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