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PowerPC 604 RISC Microprocessor Technical Summary

Figure 7. Pipeline Diagram

The common pipeline stages are as follows:

•

Instruction fetch (IF)—During the IF stage, the fetch unit loads the decode queue (DEQ) with

instructions from the instruction cache and determines from what address the next instruction

should be fetched.

•

Instruction decode (ID)—During the ID stage, all time-critical decoding is performed on

instructions in the dispatch queue (DISQ). The remaining decode operations are performed during

the instruction dispatch stage.

•

Instruction dispatch (DS)—During the dispatch stage, the decoding that is not time-critical is

performed on the instructions provided by the previous ID stage. Logic associated with this stage

determines when an instruction can be dispatched to the appropriate execution unit. At the end of

the DS stage, instructions and their operands are latched into the execution input latches or into the

unit’s reservation station. Logic in this stage allocates resources such as the rename registers and

reorder buffer entries.

•

Execute (E)—While the execution stage is viewed as a common stage in the 604 instruction

pipeline, the instruction flow is split among the six execution units, some of which consist of

multiple pipelines. An instruction may enter the execute stage from either the dispatch stage or the

execution unit’s dedicated reservation station.

At the end of the execute stage, the execution unit writes the results into the appropriate rename

buffer entry and notifies the completion stage that the instruction has finished execution.

Fetch (IF)

Decode (ID)

Dispatch (DS)

Complete (C)

Writeback (W)

(Four-instruction dispatch per clock in

any combination)

SCIU1

SCIU2

MCIU

FPU

LSU

BPU

Execute Stage

Freescale Semiconductor, Inc.

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