PowerPC 604 RISC Microprocessor Technical Summary

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Figure 2. Block Diagram—Internal Data Paths

1.2.1 Instruction Flow

Several units on the 604 ensure the proper flow of instructions and operands and guarantee the correct

update of the architectural machine state. These units include the following

•

Fetch unit—Using the next sequential address or the address supplied by the BPU when a branch

is predicted or resolved, the fetch unit supplies instructions to the eight-word instruction buffer.

•

Decode/dispatch unit—The decode/dispatch unit decodes instructions and dispatches them to the

appropriate execution unit. During dispatch, operands are provided to the execution unit (or

reservation station) from the register files, rename buffers, and result buses.

•

Branch processing unit (BPU)—In addition to providing the fetcher with predicted target

instructions when a branch is predicted (and a mispredict recovery address if a branch is incorrectly

predicted), the BPU executes all condition register logical and flow control instructions.

•

Instruction completion unit—The completion unit retires executed instructions in program order

and controls the updating of the architectural machine state.

1.2.1.1 Fetch Unit

The fetch unit provides instructions to the eight-entry instruction queue by accessing the on-chip instruction

cache. Typically, the fetch unit continues fetching sequentially as many as four instructions at a time.

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Fetch Unit

branch

(Four-instruction

Dispatch Unit

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BPU

16-Kbyte data cache

4-way, 8 words/block

Completion

Unit

instruction dispatch buses

result status buses

correction

FPR operand buses

FPR result buses

GPR operand buses

GPR result buses

LSU

MCIU

SCIU

SCIU

FPU

Result buses

Operand buses

dispatch)

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Freescale Semiconductor, Inc.

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