6

PowerPC 604 RISC Microprocessor Technical Summary

— Support for address pipelining and limited out-of-order bus transactions

— Additional signals and signal redefinition for I/O controller interface operations (referred to as

direct-store operations in the architecture specification)

•

Multiprocessing support features include the following:

— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are

provided in the instruction cache to indicate only whether a cache block is valid or invalid.

— Separate port into data cache tags for bus snooping

— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

•

Power management

— NAP mode supports full shut down and supports snooping with early indication.

— Operating voltage of 3.3

± 0.3 V

•

Performance monitor can be used to help in debugging system designs and improving software

efficiency, especially in multiprocessor systems.

•

In-system testability and debugging features through JTAG boundary-scan capability

1.2 PowerPC 604 Microprocessor Hardware

Implementation

This section provides an overview of the 604’s hardware implementation, including descriptions of the

functional units, shown in Figure 2, the cache implementation, MMU, and the system interface.

Note that Figure 2 provides a more detailed block diagram than that presented in Figure 1—showing the

additional data paths that contribute to the improved efficiency in instruction execution and more clearly

shows the relationships between execution units and their associated register files.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

AR

CH

IVE

D B

Y F

RE

ES

CA

LE

SE

MI

CO

ND

UC

TO

R,

INC

.