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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CYT4DNJBJS 데이터시트(PDF) 128 Page - Infineon Technologies AG |
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CYT4DNJBJS 데이터시트(HTML) 128 Page - Infineon Technologies AG |
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128 / 209 page  Datasheet 128 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications I2C Interface-Fast-mode Recommended I/O Configuration: GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100 GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b00, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0> = 0b1 GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0> = 0b1 HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b010, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> =0b100, CFG_SLEW_EXT/SLEW<2:0> =0b000 (Note: SID158 is not valid for GPIO_STD, HSIO_STDLN) SID150 fSCL SCL clock frequency – – 400[71] kHz SID151 tHD;STA Hold time, START condition 600 – –ns SID152 tLOW Low period of SCL 1300 – –ns SID153 tHIGH High period of SCL 600 – –ns SID154 tSU;STA Setup time for a repeated START 600 – –ns SID155 tHD;DAT Data hold time, for receiver 0 – –ns SID156 tSU;DAT Data setup time 100 – –ns SID158 tF Fall time of SCL and SDA 20 × (VDDIO_GPIO /5.5) – 300 ns Input and output Output: Only valid for GPIO_ENH, GPIO_SMC SID159 tSU;STO Setup time for STOP 600 – –ns SID160 tBUF Bus free time between START and STOP 1300 – –ns SID161 CB Capacitive load for each bus line – – 400 pF SID162 tVD;DAT Time for data signal from SCL LOW to SDA output – – 900 ns SID163 tVD;ACK Data valid acknowledge time – – 900 ns SID164 tSP Pulse width of spikes that must be suppressed by the input filter – –50 ns I2C Interface-Fast-Plus mode Recommended I/O Configuration: GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100 GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b00, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0> = 0b1 GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0> = 0b0 HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> =0b010, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> =0b100, CFG_SLEW_EXT/SLEW<2:0> =0b000 (Note: SID178 is not valid for GPIO_STD, GPIO_SMC, and HSIO_STDLN) SID170 fSCL SCL clock frequency – –1[72] MHz SID171 tHD;STA Hold time, START condition 260 – –ns SID172 tLOW Low period of SCL 500 – –ns SID173 tHIGH High period of SCL 260 – –ns SID174 tSU;STA Setup time for a repeated START 260 – –ns SID175 tHD;DAT Data hold time, for receiver 0 – –ns Table 26-10 Serial Communication Block (SCB) specifications (continued) Spec ID Parameter Description Min Typ Max Units Details/conditions |
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