CYT4DNJBJS datasheet(131/209 Pages) INFINEON

131 / 209 page

Datasheet

131

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID196A tDHI

SPI Master: MISO hold time

after SCLK capturing edge

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

SID197A CSPIM_MS

SPI Capacitive Load

–

SID198A tEN_SETUP

SSEL valid, before the first

SCLK

capturing edge

0.5 ×

(1/fSPI)

–

–ns

Min is half clock period

SID199A tEN_SHOLD

SSEL hold, after the last SCLK

capturing edge

0.5 ×

(1/fSPI)

–

–ns

Min is half clock period

SPI Interface Slave (internally clocked, GPIO and HSIO)

SID205

fSPI_INT

SPI operating frequency

–

12.5

MHz SPISlave,internallyclocked

SID206

tDMI_INT

SPI Slave: MOSI Valid before

SCLK

capturing edge

–

–ns

SPI Slave, internally clocked

SID207

tDSO_INT

SPI Slave: MISO Valid after

SCLK

driving edge, in the

internal-clocked mode

–

SPI Slave, internally clocked

SID208

tHSO_INT

SPI Slave: Previous MISO

data hold time

–

–ns

SPI Slave, internally clocked

SID209

tEN_SET-

UP_INT

SPI Slave: SSEL valid to first

SCLK

valid edge

–

–ns

SPI Slave, internally clocked

SID210

tEN_HOLD_INT SPI Slave Select active

(LOW) from last SCLK hold

–

–ns

SPI Slave, internally clocked

SID211

tEN_SET-

UP_PRE

SPI Slave: from SSEL valid,

to SCLK falling edge before

the first data bit

–

–ns

SPI Slave, internally clocked

SID212

tEN_HOLD_PRE SPI Slave: from SCLK falling

edge before the first data

bit, to SSEL invalid

–

–ns

SPI Slave, internally clocked

SID213

tEN_SETUP_CO SPI Slave: from SSEL valid,

toSCLKfallingedgeinthefirst

data bit

–

–ns

SPI Slave, internally clocked

SID214

tEN_HOLD_CO SPI Slave: from SCLK falling

edge in the first data bit, to

SSEL invalid

–

–ns

SPI Slave, internally clocked

SID215

tW_DIS_INT

SPI Slave Select inactive

time

–

–ns

SPI Slave, internally clocked

SID216

tW_SCLKH_INT SPI SCLK pulse width HIGH

–

–ns

SPI Slave, internally clocked

SID217

tW_SCLKL_INT SPI SCLK pulse width LOW

–

–ns

SPI Slave, internally clocked

SID218

tSIH_INT

SPI MOSI hold from SCLK

–

–ns

SPI Slave, internally clocked

SID219

CSPIS_INT

SPI Capacitive Load

–

pF SPISlave,internallyclocked

SPI Interface Slave (externally clocked, GPIO and HSIO)

SID220

fSPI_EXT

SPI operating frequency

–

12.5

MHz SPI Slave, externally

clocked: 12.5 Mbps

SID221

tDMI_EXT

SPI Slave: MOSI Valid before

SCLK

capturing edge

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

Table 26-10

Serial Communication Block (SCB) specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max Units

Details/conditions

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