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CYT4DNJBJS 데이터시트(PDF) 130 Page - Infineon Technologies AG

부품명 CYT4DNJBJS
상세설명  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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제조업체  INFINEON [Infineon Technologies AG]
홈페이지  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS 데이터시트(HTML) 130 Page - Infineon Technologies AG

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Datasheet
130
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
SID195
tVSS
SPI Master: MOSI valid after
SSEL falling edge (CPHA=0)
–
–
12
ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 12.5 Mbps
for instances on GPIO_STD,
GPIO_ENH, GPIO_SMC
SID196
tDHI
SPI Master: MISO hold time
after SCLK capturing edge
0
–
–ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 12.5 Mbps
for instances on GPIO_STD,
GPIO_ENH, GPIO_SMC
SID198
tEN_SETUP
SSEL valid, before the first
SCLK
capturing edge
0.5 ×
(1/fSPI)
–
–ns
Min is half clock period
SID199
tEN_SHOLD
SSEL hold, after the last SCLK
capturing edge
0.5 ×
(1/fSPI)
–
–ns
Min is half clock period
SID197
CSPIM_MS
SPI Capacitive Load
–
–
20
pF
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1, HSIO)
SID190A fSPI
SPI operating frequency
–
–20
MHz Donotusehalf-clockmode:
LATE_MISO_SAMPLE = 0
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) - 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz.
for instances on HSIO_STD
SID191A tDMO
SPI Master: MOSI valid after
SCLK driving edge
–
–9
ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz
for instances on HSIO_STD
SID192A tDSI
SPI Master: MISO valid
before SCLK capturing edge
25
–
–ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz
for instances on HSIO_STD
SID193A tHMO
SPI Master: Previous MOSI
data hold time
0
–
–ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz
for instances on HSIO_STD
SID194A tW_SCLK_H_L SPI SCLK pulse width HIGH
or LOW
0.4 ×
(1/fSPI)
0.5 ×
(1/fSPI)
0.6 ×
(1/fSPI)
ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz
for instances on HSIO_STD
SID195A tVSS
SPI Master: MOSI valid after
SSEL falling edge (CPHA=0)
–
–
12
ns
SPI Master (Full-clock
mode:LATE_MISO_SAMPLE
= 1) – 20 Mbps
For 20 Mbps, SCB operating
frequency (fSCB) must be
configured to 80 MHz
for instances on HSIO_STD
Table 26-10
Serial Communication Block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units
Details/conditions



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