LDO Electrical Characteristics

Unless otherwise specified: C

standard typeface apply for T

operation, −30˚C to +85˚C. (Note 3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

OUT

Output Voltage, V

I

2.76

2.85

2.93

V

∆V

OUT

Output Voltage Tolerance

I

−2

−3

2

3

%of

V

OUT(nom)

Line Regulation Error (Note 6)

V

1mA

−0.15

0.15

%/V

Load Regulation Error (Note 7)

I

−0.01

0.01

%/mA

Output AC Line Regulation

V

I

1.5

mV

PP

PSRR

Power Supply Rejection Ratio (Note

15)

V

f = 1 kHz, I

40

dB

V

f = 10 kHz, I

30

∆V

DO

Dropout Voltage (Note 8)

I

1

mV

I

20

I

35

I

60

110

I

SC

Short Circuit Current Limit

V

State)

750

mA

T

ON

Turn-On Time (Notes 9, 15)

30

200

µs

ρn (1/f)

Output Noise Density

f = 1 kHz, C

0.6

µV/

e

n

Output Noise Voltage

BW = 10 Hz to 100 kHz, C

45

µVrms

Output

Capacitor

Output Filter Capacitance (Note 10)

V

I

0.7

1.0

22

µF

Output Filter Capacitance ESR

(Note 11)

V

I

5

500

m

Ω

Thermal

Shutdown

Thermal Shutdown Temperature

(Notes 12, 15)

V

I

160

˚C

Thermal Shutdown Hysteresis (Note

15)

20

˚C

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.

Note 2: IEC61000-4-2 level 4 ESD tolerance applies to VDDB, D0_B–D3_B, CMD_B, CLK_B, WP and CP pins only. Device is tested in application (common

Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are reference to ground unless otherwise

specified.

Note 5: Input signal for test purpose is defined as: A side – 0V to 1.8V with 2ns rise time (20%-70%) and B side – 0V to 2.85V with 2ns rise time (20%-70%)

Note 6: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.

Note 7: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.

Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply

for input voltages below 2.7V.

Note 9: Turn-on time is that between when the enable input is high an the output voltage just reaching 95% of its nominal value.

Note 10: Range of capacitor value for which the device will remain stable. This electrical specification is guaranteed by design.

Note 11: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.

Note 12: The built-in thermal shut-down of the LDO is also used to put all A and B outputs in tri-state mode.

Note 13: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).

Note 14: Unused inputs must be terminated.

Note 15: This electrical specification is guaranteed by design.

Note 16: The SD/MMC card specification calls for a total of 30 pF capacitance. A load of 15 pF is internal to the LP3929, so the external load capacitance on the

B side should comprise the remaining (15 pF or less).

Timing Diagrams

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