S71GS256 datasheet(11/195 Pages) SPANSION

11 / 195 page

December 17, 2004 S71GS256/128N_00_A0

Ad vance

Info rmat i o n

Input/Output Descriptions

A23-A0

24 Address inputs (256 Mb)

A22-A0

23 Address inputs (128 Mb)

DQ15-DQ0

Data input/output

OE#

Output Enable input. Asynchronous relative to CLK

for the Burst mode.

WE#

Write Enable input.

VSS

Ground

No Connect; not connected internally

F-RST#

Hardware reset input. Low = device resets and

returns to reading array data

WP#/ACC

Hardware write protect input / programming

acceleration input.

R-CE1#

Chip-enable input for pSRAM.

ZZ#

pSRAM Sleep mode

CRE

Configuration Register Enable. CRE is used only for

power savings, but does not enable burst

operations.

F1-CE#

Chip-enable input for Flash 1.

F-VCC

Flash 3.0 Volt-only single power supply.

R-VCC

pSRAM Power Supply.

R-UB#

Upper Byte Control (pSRAM).

R-LB#

Lower Byte Control (pSRAM).

RFU

Reserved for future use.

RY/BY#

Ready/Busy output.

F-VIO

Flash Input/Output Buffer Power Supply

R-VIO

pSRAM Input/Output Buffer Power Supply

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