87421 Data Sheet

©2016 Integrated Device Technology, Inc

June 24, 2016

8

FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVDS DRIVER

3.3V

R1

50

R3

50

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

R2

50

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

R3

125

R2

84

Zo = 50 Ohm

3.3V

R4

125

LVPECL

R1

84

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 3A to 3F show interface examples

for the HiPerClockS CLK/nCLK input driven by the most common

driver types.The input interfaces suggested here are examples only.

FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY AN IDT OPEN EMITTER

HIPERCLOCKS LVHSTL DRIVER

Please consult with the vendor of the driver component to confirm

the driver termination requirements. For example in Figure 3A, the

input termination applies for IDT HiPerClockS open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor, use

their termination recommendation.

1.8V

R2

50

Input

LVHSTL Driver

ICS

HiPerClockS

R1

50

LVHSTL

3.3V

Zo = 50 Ohm

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V HCSL DRIVER

Zo = 50 Ohm

R1

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

FIGURE 3F.

HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 2.5V SSTL DRIVER