÷1/÷2 Differential-to-LVDS

Clock Generator

87421

Data Sheet

©2016 Integrated Device Technology, Inc

June 24, 2016

1

GENERAL DESCRIPTION

The

87421I

is

a

high

perf or mance

÷1/÷2

Differential-to-LVDS Clock Generator. The CLK, nCLK

pair can accept most standard

diff erential input

levels. The 87421I is characterized to operate from a 3.3V

power supply. Guaranteed part-to-part skew characteristics

make the 87421I ideal for those clock distribution applications

demanding well defined performance and repeatability.

FEATURES

• One differential LVDS output

• One differential CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential input lev-

els: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum clock input frequency: 1GHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVDS levels with resistor bias on nCLK input

• Part-to-part skew: 500ps (maximum)

• Propagation delay: 1.7ns (maximum)

• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)

• Full 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• For functional replacement device use 87321

BLOCK DIAGRAM

PIN ASSIGNMENT

87421I

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

CLK

nCLK

MR

F_SEL

1

2

3

4

VDD

Q

nQ

GND

8

7

6

5

Q

nQ

CLK

nCLK

MR

F_SEL

0

1

÷1

÷2

R

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017