ST7789V2 datasheet(48/319 Pages) SITRONIX

48 / 319 page

ST7789V2

Version 1.0

Page 48 of 319

2016/11

Sitronix Confidential

The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or

disclosed in whole or in part without prior written permission of Sitronix.

7.4.5

Reset Timing:

Display

status

During reset

Initial condition

(Default for H/W reset)

RESX

Normal operation

Shorter than 5us

Figure 7 Reset Timing

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25

℃

Related Pins

Symbol

Parameter

MIN

MAX

Unit

RESX

TRW

Reset pulse duration

TRT

Reset cancel

5 (Note 1, 5)

120 (Note 1, 6, 7)

Table 9 Reset Timing

Notes:

1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to

registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX.

2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:

RESX Pulse

Action

Shorter than 5us

Reset Rejected

Longer than 9us

Reset

Between 5us and 9us

Reset starts

3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120

ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode.) and then return to Default condition

for Hardware Reset.

4. Spike Rejection also applies during a valid reset pulse as shown below:

ST7789V2 데이터시트(PDF) 48 Page - Sitronix Technology Co., Ltd.

ST7789V2 데이터시트(HTML) 48 Page - Sitronix Technology Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL