AD9923ABBCZ datasheet(15/88 Pages) AD

15 / 88 page

AD9923A

Rev. 0 | Page 15 of 88

Table 10. Precision Timing Edge Locations

Quadrant

Edge Location (Decimal)

0 to 11

000000 to 001011

12 to 23

16 to 27

010000 to 011011

III

24 to 35

32 to 43

100000 to 101011

36 to 47

48 to 59

110000 to 111011

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

CLI

tCLIDLY

POSITION

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY = 6ns TYP).

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS:

1RG RISING EDGE.

2RG FALLING EDGE.

3SHP SAMPLE LOCATION.

4SHD SAMPLE LOCATION.

5HL RISING EDGE POSITION.

6HL FALLING EDGE POSITION.

7H1 RISING EDGE POSITION.

8H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

9H3 RISING EDGE POSITION.

10H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).

910

Figure 18. High Speed Clock Programmable Locations

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