AD9981SLASHPCB datasheet(22/44 Pages) AD

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AD9981

Preliminary Technical Data

Rev. 0 | Page 22 of 44

Mode Descriptions

•

4:4:4—All channels come out with their 10 data bits at the

same time. Data is aligned to the negative edge of the clock

for easy capture. This is the normal 30-bit output mode for

RGB or 4:4:4 YCbCr.

•

4:2:2—Red and green channels contain 4:2:2 formatted

data (20 pins) with Y data on the green channel and Cb, Cr

data on the red channel. Data is aligned to the negative

edge of the clock. The blue channel contains the secondary

channel with Cb, Y, Cr, Y formatted 4:2:2 DDR data. The

data edges are aligned to both edges of the pixel clock, so

use of the 90° clock may be necessary to capture the DDR

data.

•

4:4:4 DDR—This mode puts out full 4:4:4 data on 15 bits of

the red and green channels, thus saving 15 pins. The first

half (RGB [14:0]) of the 30-bit data is sent on the rising

edge and the second half (RGB [29:15]) is sent on the

falling edge. DDR 4:2:2 data is sent on the blue channel, as

in 4:2:2 mode.

RGB [29:0] = R [9:0] + G [9:0] + B [9:0], so RGB [29:15] =

R [9:0] + G [9:5] and RGB [14:0] = G [4:0] + B [9:0]

Table 11. Output Formats

Port

Red

Green

Blue

Bit

4:4:4

Red/Cr

Green/Y

Blue/Cb

4:2:21

Cb, Cr

DDR 4:2:2

↑ Cb, Cr ↓ Y,Y

DDR

↑2 G [4:0]

DDR

↑ B [9:0]

N/A

DDR 4:2:2

↑ Cb,Cr

4:4:4

DDR

↓ R [9:0]

DDR

↓ G [9:5]

N/A

DDR 4:2:2

↓ Y,Y

1 For 4:2:2 modes, the first item in the list is the first pixel after Hsync.

2 Arrows in the table indicate clock edge. Rising edge of clock =

↑, falling edge = ↓.

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