CDB53L21 datasheet(15/66 Pages) CIRRUS

15 / 66 page

DS700PP1

CS53L21

7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are

settled.

8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.

9. See“Master” on page 30.

10. “MCLK” refers to the external master clock applied.

Master Mode (Note 9)

Output Sample Rate (LRCK)

All Speed Modes

(Note 10)

-Hz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-52

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

Parameters

Symbol

Min

Max

Units

MCLK

128

-----------------

th(SK-SDO)

MSB

MSB-1

LRCK

SCLK

SDOUT

td(MSB)

ts(LK-SK)

ts(SDO-SK)

Figure 3. Serial Audio Interface Slave Mode Timing

th(SK-SDO)

MSB

MSB-1

LRCK

SCLK

SDOUT

td(MSB)

ts(SDO-SK)

Figure 4. Serial Audio Interface Master Mode Timing

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