CDB53L21 datasheet(19/66 Pages) CIRRUS

19 / 66 page

DS700PP1

CS53L21

POWER CONSUMPTION

See (Note 17)

17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =

48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-

ter/slave operation.

18. RESET pin 25 held LO, all clocks and data lines are held LO.

19. RESET pin 25 held HI, all clocks and data lines are held HI.

20. VL current will slightly increase in master mode.

Power Ctl. Registers

Typical Current (mA)

Operation

02h

03h

iVA

iVD

iVL

(Note 20)

Total

Power

(mWrms)

Off (Note 18)

xxxx xxxxxx 1.8

2.5

Standby (Note 19)

xxxx xx1 xxx 1.8

0.01

0.02

0.05

2.5

0.01

0.03

0.10

Mono Record

ADC 1111 100111 1.8

1.85

2.03

0.03

7.05

2.5

2.07

3.05

0.05

12.94

PGA to ADC 1110 100111 1.8

2.35

2.03

0.03

7.95

2.5

2.58

3.08

0.05

14.29

MIC to PGA to ADC

(with Bias)

1110 100100 1.8

3.67

2.05

0.03

10.36

2.5

3.95

3.09

0.05

17.71

MIC to PGA to ADC

(no Bias)

1110 100101 1.8

3.27

2.03

0.03

9.61

2.5

3.52

3.08

0.05

16.62

Stereo Record

ADC 1111 000111 1.8

2.69

2.12

0.03

8.72

2.5

2.93

3.18

0.04

15.40

PGA to ADC 1100 000111 1.8

3.65

2.12

0.03

10.45

2.5

3.91

3.17

0.04

17.84

MIC to PGA to ADC

(no Bias)

1100 000001 1.8

5.48

2.11

0.03

13.73

2.5

5.76

3.17

0.04

22.45

CDB53L21 데이터시트(PDF) 19 Page - Cirrus Logic

CDB53L21 데이터시트(HTML) 19 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

데이터시트 다운로드

링크 URL