CS4525 datasheet(82/91 Pages) CIRRUS

82 / 91 page

DS726A1

CS4525

9.19

Interrupt Register (Address 60h)

Bits [7:4] in this register are read only. A ‘1’b in these bit positions indicates that the associated condition has oc-

curred at least once since the register was last read. A ‘0’b indicates that the associated condition has not occurred

since the last reading of the register. Reading the register resets bits to [7:4] ‘0’b. These bits are considered “edge-

trigger” events. The operation of these 4 bits is not affected by the interrupt mask bits and the condition of each bit

can be polled instead of generating an interrupt as required.

9.19.1

SRC Lock State Transition Interrupt Bit (SRCLock)

Default = 0

Function:

This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or

from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC

to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will

cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read

of this register.

If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go

active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status reg-

ister.

9.19.2

ADC Overflow Interrupt Bit (ADCOvfl)

Default = 0

Function:

This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525

ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read

of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this

If this bit is set, indicating an ADC over-range condition, and the ADCOvflM bit is set, the INT pin will go

active. To determine the current overflow state of the ADC, read the ADCOvflSt bit in the interrupt status

9.19.3

Channel Overflow Interrupt Bit (ChOvfl)

Default = 0

Function:

This bit is read only. When set, indicates that the magnitude of an output sample on channel 1, 2, or 3 has

exceeded full scale and has been clipped to positive or negative full scale as appropriate since the last

read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of

this register.

SRCLock

ADCOvfl

ChOvfl

AmpErr

SRCStateM

ADCOvflM

ChOvflM

AmpErrM

SRCLock Setting

SRC Lock State Change Status

0 .......................................... SRC lock state unchanged since last read of this register.

1 .......................................... SRC lock state changed since last read of this register.

ADCOvfl Setting

ADC Overflow Event Status

0 .......................................... ADC overflow condition has not occurred since last read of this register.

1 .......................................... ADC overflow condition has occurred since last read of this register.

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