CS4525 datasheet(84/91 Pages) CIRRUS

84 / 91 page

DS726A1

CS4525

9.19.7

Mask Bit for Channel X Overflow (ChOvflM)

Default = 0

Function:

This bit serves as a mask for the channel overflow interrupt source. If this bit is set, the ChOvfl interrupt

is unmasked, meaning that if the ChOvfl bit is set, the INT pin will go active. If the ChOvflM bit is cleared,

the ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the ChO-

vfl and ChXOvflSt bits will continue to reflect the overflow state of the individual channels.

9.19.8

Mask Bit for Amplifier Error (AmpErrM)

Default = 0

Function:

This bit serves as a mask for the amplifier error interrupt sources. If this bit is set, the AmpErr interrupt is

unmasked, meaning that if the AmpErr bit is set, the INT pin will go active. If the AmpErrM bit is cleared,

the AmpErr condition is masked, meaning that its occurrence will not affect the INT pin. However, the Am-

pErr and the amplifier error bits in the amplifier error status register will continue to reflect the status of the

amplifier error conditions.

9.20

Interrupt Status Register (Address 61h) - Read Only

All bits in this register are considered “level-trigger” events, meaning as long as a condition continues, the corre-

sponding bit will remain set. These status bits are not affected by the interrupt mask bit and the condition of each

bit can be polled. These bits will not be cleared following a read to this register, nor can they be written to cause an

interrupt condition.

9.20.1

SRC State Transition (SRCLockSt)

Default = 0

Function:

This bit is read only and reflects the current lock state of the SRC. When set, indicates the SRC is currently

locked. When cleared, indicates the SRC is currently unlocked.

ChOvflM Setting

ChOvfl INT Pin Mask State

0 .......................................... ChOvfl condition masked.

1 .......................................... ChOvfl condition un-masked.

AmpErrM Setting

AmpErr INT Pin Mask State

0 .......................................... AmpErr condition masked.

1 .......................................... AmpErr condition un-masked.

SRCLockSt

ADCOvflSt

Ch3OvflSt

Ch2OvflSt

Ch1OvflSt

RampDone

Reserved

SRCLockSt Setting

SRC Lock State

0 .......................................... SRC is currently unlocked.

1 .......................................... SRC is currently locked.

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