CS4525 datasheet(83/91 Pages) CIRRUS

83 / 91 page

DS726A1

CS4525

If this bit is set, indicating a channel over-range condition, and the ChOvflM bit is set, the INT pin will go

active. To determine the current overflow state of each channel, read the ChXOvflSt bits in the interrupt

status register.

9.19.4

Amplifier Error Interrupt Bit (AmpErr)

Default = 0

Function:

This bit is read only. When set, indicates that an error was detected in the power amplifier section since

the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a

read of this register. This bit is the logical OR of all the bits in the amplifier error status register. Read the

amplifier error status register to determine which condition occurred.

If this bit is set, indicating an amplifier stage error condition, and the AmpErrM bit is set to a ‘1’b, the INT

pin will go active. To determine the actual current state of the amplifier error condition, read the amplifier

error status register.

9.19.5

Mask Bit for SRC State (SRCLockM)

Default = 0

Function:

This bit serves as a mask for the SRC status interrupt source. If this bit is set, the SRCLock interrupt is

unmasked, meaning that if the SRCLock bit is set, the INT pin will go active. If the SRCLockM bit is

cleared, the SRCLock condition is masked, meaning that its occurrence will not affect the INT pin. How-

ever, the SRCLock and SRCLockSt bits will continue to reflect the lock status of the SRC.

9.19.6

Mask Bit for ADC Overflow (ADCOvflM)

Default = 0

Function:

This bit serves as a mask for the ADC overflow interrupt source. If this bit is set, the ADCOvfl interrupt is

unmasked, meaning that if the ADCOvfl bit is set, the INT pin will go active. If the ADCOvflM bit is cleared,

the ADCOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the

ADCOvfl and ADCOvflSt bits will continue to reflect the overflow state of the ADC.

ChOvfl Setting

Channel Overflow Event Status

0 .......................................... A channel overflow condition has not occurred since last read of this register.

1 .......................................... A channel overflow condition has occurred since last read of this register.

AmpErr Setting

Amplifier Error Event Status

0 .......................................... An amplifier error condition has not occurred since last read of this register.

1 .......................................... An amplifier error condition has occurred since last read of this register.

SRCLockM Setting

SRCLock INT Pin Mask State

0 .......................................... SRCLock condition masked.

1 .......................................... SRCLock condition un-masked.

ADCOvflM Setting

ADCOvfl INT Pin Mask State

0 .......................................... ADCOvfl condition masked.

1 .......................................... ADCOvfl condition un-masked.

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