LPC804 datasheet(46/89 Pages) NXP

46 / 89 page

LPC804

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Product data sheet

Rev. 2.1 — 25 July 2023

46 of 87

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller

12.2.1 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG.

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code accessing the peripheral is executed. Measured on a typical

sample at Tamb = 25 C.

The supply currents are shown for system clock frequencies of 12 MHz and 15 MHz.

Table 13. Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in μA

Notes

System clock frequency =

n/a

12 MHz

15 MHz

FRO

FRO = 12MHz. FRO output disabled.

BOD

Independent of main clock frequency.

Flash

LPOsc

FRO; independent of main clock frequency.

GPIO + pin interrupt

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

SWM

IOCON

CTimer

MRT

WWDT

I2C0

I2C1

SPI0

USART0

USART1

Comparator ACMP

ADC

Digital controller only. Analog portion of the

ADC disabled in the PDRUNCFG register.

Combined analog and digital logic. ADC

enabled in the PDRUNCFG register and

LPWRMODE bit set to 1 in the ADC CTRL

Combined analog and digital logic. ADC

enabled in the PDRUNCFG register and

LPWRMODE bit set to 0 in the ADC CTRL

DAC

Capacitive Touch

PLU

118

149

CRC

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