Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

5. Pinning information

5.1. Pinning

74HC161

MR

VCC

CP

TC

D0

Q0

D1

Q1

D2

Q2

D3

Q3

CEP

CET

GND

PE

aaa-024396

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT109-1 (SO16)

74HC161

MR

VCC

CP

TC

D0

Q0

D1

Q1

D2

Q2

D3

Q3

CEP

CET

GND

PE

aaa-024397

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 6. Pin configuration SOT403-1 (TSSOP16)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

MR

1

asynchronous master reset (active LOW)

CP

2

clock input (LOW-to-HIGH, edge-triggered)

D0, D1, D2, D3

3, 4, 5, 6

data input

CEP

7

count enable input

GND

8

ground (0 V)

PE

9

parallel enable input (active LOW)

CET

10

count enable carry input

Q0, Q1, Q2, Q3

14, 13, 12, 11

flip-flop output

TC

15

terminal count output

VCC

16

supply voltage

74HC161

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Product data sheet

Rev. 5 — 16 March 2021

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